In semiconductor devices, sizes of patterns formed on a chip and/or distances between adjacent patterns may be decreased in order to realize higher degrees of integration. When the sizes of the patterns are decreased, the patterns may have an increased resistance. Thus, increasing the degree of integration by decreasing the sizes of the patterns may have its limits. Accordingly, instead of decreasing the sizes of the patterns, stacked semiconductor devices in which unit elements (such as metal-oxide-semiconductor (MOS) transistors) are stacked on a substrate in order to realize a higher degree of integration have been developed.
More particularly, a static random access memory (SRAM) device may have a relatively large cell size because the cell of the SRAM device includes six transistors. When the size of the cell is increased, the number of chips manufactured on a substrate may be decreased, so that the manufacturing cost of the SRAM device may be increased. Thus, transistors included in a cell may be vertically stacked so that the cell in the SRAM device may have a decreased size.
A single crystalline silicon layer serving as a channel may be formed on a single crystalline silicon substrate for forming a stacked memory device. The single crystalline silicon layer may include relatively few crystal defects in order for the single crystalline silicon layer to serve as a channel in a transistor. Additionally, the single crystalline silicon layer may have a relatively planar flat upper surface so that patterns on the single crystalline silicon layer may not be tilted.
A method of forming a single crystalline silicon layer is disclosed in U.S. Pat. No. 5,494,823 issued to Kobayashi. According to U.S. Pat. No. 5,494,823, an amorphous silicon layer is formed on a single crystalline silicon substrate, and the amorphous silicon layer is thermally treated at a temperature of about 600° C. to about 620° C. to be transformed into a single crystalline silicon layer. When the amorphous silicon layer is formed, nitrogen gas is used.
However, when the amorphous silicon layer is transformed into the single crystalline silicon layer by the thermal treatment, protrusions may be formed on an upper portion of the single crystalline silicon layer so that the single crystalline silicon layer may have relatively poor surface roughness characteristics. Thus, some recent research has been focused on developing methods of forming a single crystalline silicon layer having a substantially flat upper surface. For example, a method of forming a single crystalline silicon layer having a high degree of flatness by oxidizing a top surface of the single crystalline silicon layer to form an oxide layer and then removing the oxide layer is disclosed in Japanese Laid-Open Patent Publication No. 1998-106951. However, protrusions on an upper portion of a single crystalline silicon layer may not be sufficiently removed by the method disclosed in Japanese Laid-Open Patent Publication No. 1998-106951.